Progressive development of handheld and multimedia applications accelerates the demand for unified memory technology, replacing data/code (flash, ROM) and execution (DRAM and SRAM) storage media using a single die. MRAM (Magnetic Random Access Memory) offers the unique combination of non-volatility, high endurance and excellent random access speed to become such a new prevalent memory technology. MRAM is non-volatile memory that uses magnetism rather than electrical power to store data.
The major structure of a typical MRAM cell is the MTJ (Magnetic Tunnel Junction) stack, as well as one transistor. The MTJ stack is composed of a pinned magnetic layer, a tunnel barrier, and a free magnetic layer, all sandwiched between top and bottom electrodes. Electrons, spin polarized by the magnetic layer, traverse the tunnel barrier. A parallel alignment of the pinned and free magnetic layers results in a low resistance state, while an anti-parallel alignment results in a high resistance state. In MRAM cell metal routing, the word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line. The memory cell stores a bit (or multiple bits) of information as an orientation of a magnetization. The magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of “0” and “1”.
The conventional MRAM cell also includes a thin oxide pass transistor, which is electrically connected to the MTJ stack by the bottom or top electrode conductors. As for data input (“writing” to the MRAM cell), a wider bit line and write word line are often used on the MTJ stack top or bottom portion for data writing. As future MRAM cell size continues to shrink, several limiting factors become prevalent. Included in these factors are MTJ stack size, the size of the under-layer write word line, and the size of the connection path between the bottom electrode and the pass transistor.
For the connection path of the MTJ stack bottom electrode to the pass transistor, the gating factor is the minimum area of metal landing pad that located in the same metal layer with the under-layer write word line. In conventional structures, this landing pad is found in the connection from the bottom electrode to an under-layer metal (near the pass transistor), using vias on either side of it. However, considering metal rule continuous shrinkage, a challenge is faced on process margin tradeoff between line-space isolation and minimum landing pad opening (a hole-like shape (damascene process)). Specifically, the area shrinkage (area×S2 factor) factor is 1× order faster than the line shrinkage (pitch×S factor) factor. This 2-D effect induces a process margin concern from conflict requirements of line shape (bridge concern: middle or low exposure energy) and hole shape (blind concern: higher exposure energy). This results in landing margin concern on the upper-layer via hole to this metal layer, or this metal layer to the bottom-layer via hole. So as device size continues to decrease, this metal landing pad area and the write word line width will become the bottleneck of the cell size shrinkage, for example, in 90 nm and beyond.